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Germanium telluride can be used as a material to prepare a sulfide semiconductor mask for photolithography.

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Author : Jazmyn
Update time : 2024-03-19 09:10:21

It is characterized in that the material of the sulfide semiconductor mask is germanium telluride, germanium antimony telluride, silver indium antimony tellurium, antimony telluride or antimony. Due to the third-order nonlinear effect of the material, the sulfide semiconductor mask material of the present invention can greatly reduce the light spot or etching line width. The etching point or etching line width is 1/3-1/6 of the light spot diffraction limit. The effect of using metal indium (In) (60%) is more obvious, and the required laser power is also greatly reduced.

 

The "big" trouble with semiconductor material masks

Recently, a video showing ASML's high numerical aperture (High-NA) EUV lithography machine entering an Intel factory has attracted widespread attention in the semiconductor industry. Because this is related to whether Moore's Law can continue to develop. For chip manufacturing below 2nm, the 0.55 high-NA EUV lithography machine with a higher numerical aperture plays a vital role.

However, an indisputable fact is that high-NA EUV lithography machines are much more complex than the previous generation EUV lithography machines, which will inevitably bring new challenges to chip design and manufacturing. Intel, as the first company to purchase high-NA EUV lithography machines, recently revealed in an interview with More than Moore that its CEO Pat Kissinger wants to use a larger mask to make the high-NA EUV lithography machines more effective. Great economic benefits.

The cost of an EUV lithography machine is approximately US$250 million, while the cost of this high numerical aperture (High-NA) EUV lithography machine is approximately US$400 million. Is it worth such an expensive investment? We all know that Moore's Law is essentially an economic law. Moore's Law states that the number of transistors on an integrated circuit will double every 18 months while the cost of the chip will drop by half. This has promoted the continuous advancement of chip manufacturing technology and made electronic products more popular.

 

Will the next step in chip shrinkage (or Moore's Law) be to create larger masks?

What are the reasons?

As we all know, in the current advanced process chip manufacturing process, photolithography is one of the most critical process steps in chip manufacturing, and its accuracy directly affects the yield and performance of the chip. To continue shrinking logic and memory nodes, lithography tools must be able to print smaller features. By increasing the numerical aperture, high-NA EUV lithography machines can achieve smaller feature sizes and higher pattern density, which can be said to be the "hope of the whole village."

Although the high-NA EUV lithography machine brings benefits such as higher resolution, it also brings other disadvantages. Compared with ordinary EUV lithography machines, the biggest change of high-NA EUV lithography machines is that their exposure field of view is halved (that is, the wafer area exposed in a single exposure step is half smaller).

High-NA EUV uses an anamorphic lens, and there is a difference in magnification in the X and Y directions. The reduction ratio of the mask size remains unchanged at 4 times in the horizontal direction. Still, it is reduced by 8 times in the vertical direction, which results in a reduction in the exposure area. Halfway through, it becomes 26 x 16.5 mm. The current industry standard EUV exposure area is 26 x 33 mm. This means that the area of the high-NA EUV lithography machine mask that can be mapped to the wafer is reduced by half, forming so-called half-field imaging. Therefore, patterning a single wafer requires twice the number of exposures, which also doubles the time to print the wafer.

One solution is to split the design into two masks and sew them together, but this is a challenging task. Imagine trying to print a photo from two adjacent negatives to produce a seamless image, and it isn't easy.

Moreover, in order to meet the needs of applications with strong computing power requirements, such as AI and 5G, the industry is moving in the direction of large chips, and many current Nvidia chips cannot be printed using High-NA EUV. This challenge will have to be solved sooner or later.

 

Therefore, the industry began to consider another option: producing larger masks. The mask is a key element in the photolithography process. Predefined patterns are on the mask, which is transferred to the wafer through exposure light during the process to form circuit patterns. The accuracy and size of the mask are directly related to the quality and throughput efficiency of the final product.

Intel, as the first to "eat crabs," is taking the lead in pushing the semiconductor industry to adopt larger mask size standards. Although Intel said that compared with traditional double exposure technology, the single exposure technology of the high-NA EUV lithography machine can reduce process steps, improve production efficiency, and reduce production costs. Furthermore, High-NA EUV lithography also offers advantages over other multi-patterning and self-aligned technologies.

But Gelsinger also noted that larger mask sizes could make EUV more economical overall.

The standard mask size currently used by EUV lithography machines is 6 x 6 inches. Intel hopes that ASML and Intel's internal mask manufacturing team can develop larger masks to double the size to 6 x 12 inches and return to the standard exposure area size. This would avoid the complex and difficult stitching process when producing larger chips.

 

In summary, using a larger mask size can bring the following advantages:

Increased throughput: Exposing more wafer area in one step can increase throughput.

Reduce costs: Reducing exposure steps reduces costs.

Eliminate design constraints: Larger mask sizes can give chipmakers more flexibility when designing chips.
 

It is reported that Intel's acquisition of high-NA EUV lithography equipment will initially be used to learn and master the technology. It is planned to be implemented on the Intel 18A process node in the next two to three years (although not for mass production) and eventually adopted. Its Intel 14A manufacturing process enables high-volume manufacturing.

 

Many challenges

However, increasing the mask size is a huge technical challenge and has many knock-on effects because the current mask infrastructure is designed around a 6x6-inch square reticle infrastructure. Scaling the mask size to 6x12 may require new photoresists, metrology, film materials, masks, inspection tools, etc., inevitably requiring significant re-investment in infrastructure. Producing defect-free mask blanks is an obstacle to low numerical aperture EUV development even at current dimensions, and doubling them.

In essence, the supply chain of the entire mask industry must change, which can be said to affect the whole body. The relevant industrial chains mainly include:

Mask writer: IMS will likely support the 6 x 12-inch format to a large extent. An important manufacturer of EUV mask writers is also Applied Materials.

Photomask: Usually, a mask is made of a 6 x 6 inch glass substrate coated with a metal film and photosensitizer. Making a 6 x 12-inch mask is more complicated than making a standard 6 x 6 inch mask because it requires a larger glass substrate and more materials. At the same time, the requirements for precision and uniformity in the manufacturing process are higher because any small defects may be magnified on large-size masks. Additionally, handling and aligning larger masks will be more challenging, requiring special equipment and techniques.

Mask protectors: These are thin films (pellicles) that cover photomasks during the chip manufacturing process. Its main purpose is to protect the photomask from damage by dust, debris, and other contaminants. These contaminants can cause photomask defects, which can lead to reduced chip yield. Similar to photomasks, 6x12 film development will be more challenging than 6x6 film.

Mask inspection equipment: Lasertec released the actinic pattern mask inspection (APMI) system ACTIS in 2019 and has since offered it as an actinic inspection solution for EUV mask inspection. Lasertec is already researching the next generation of high-NA EUV lithography inspection equipment, which is expected to support 6 x 12-inch masks (if you are interested, you can check out "Actinic pattern mask inspection for high-NA EUV lithography").

 

As a manufacturer of lithography machines, ASML needs to adapt to changes in larger mask sizes. This is a challenging task as it involves many technical and engineering adjustments.

In the era of high-NA EUV, the complexity and interdependence between various industrial chains have reached a new level. Just as EUV requires ecosystem integration, bringing high-NA EUV lithography into production requires deep collaboration and partnerships. Learn how to leverage this to drive the next decade of semiconductor innovation.

Big chip? Small chip? Thoughts on future chip design

From the perspective of chip design companies, if high-NA EUV lithography machines are to be used to produce larger chips, the industry may face the challenge of redesigning chips to adapt to new technologies. There are several trends worth paying attention to:

Moving toward chipsets: Because of the cost and complexity of making large-sized chips, manufacturers may re-evaluate the design of individual large chips. By optimizing the design, a large chip can be divided into multiple small chips, each of which performs a specific function. These small chips can be integrated through packaging technology at a later stage to achieve the same or better performance than a single large chip. This not only reduces production difficulty but also increases output flexibility and overall performance.

Development of advanced chip packaging technologies: As chip sizes shrink, advanced packaging technologies have become critical as they allow different chip components to be integrated into smaller spaces without sacrificing performance. Through packaging methods such as multi-chip modules (MCM) or chip stacking technology, high-performance computing and storage can be achieved while optimizing power efficiency and signal transmission. Advances in these technologies are key to overcoming the challenges High-NA EUV encounters in making large chips.

 

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